Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-25
2010-10-19
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
07818642
ABSTRACT:
In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed.
REFERENCES:
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patent: 7185253 (2007-02-01), Mitra et al.
patent: 2004/0249615 (2004-12-01), Grzeszczuk et al.
patent: 2007/0079300 (2007-04-01), Du et al.
patent: 1196844 (1985-12-01), None
Kim Kee Sup
Kovacs Avi
Zhang Ming
Ellis Kevin L
Gandhi Dipakkumar
Intel Corporation
Trop Pruner & Hu P.C.
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