Generation of reproducible random initial states in RTL simulato
Generation of test vectors for testing electronic circuits...
Generator/compactor scan circuit low power adapter
Generator/compactor scan circuit low power adapter with counter
Generic debug external connection (GDXC) for high...
Global transition scan based AC method
Globally distributed scan blocks
Graphical editor for defining memory test sequences
Graphical user interface for testability operation
Handling a 1-hot multiplexer during built-in self-testing of...
Hardware tracing/logging for highly integrated embedded controll
Hardware verification scripting
Hierarchical access of test access ports in embedded core...
Hierarchical built-in self-test for system-on-chip design
Hierarchical creation of vectors for quiescent current...
Hierarchical test access port architecture for electronic...
Hierarchical test circuit structure for chips with multiple...
Hierarchical test response compaction for a plurality of...
Hierarchically-controlled automatic test pattern generation
High speed ATPG testing circuit and method