Globally distributed scan blocks

Details Globally distributed scan blocks Globally distributed scan blocks

2000-09-19

2003-12-16

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C365S201000

Reexamination Certificate

active

06665828

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to integrated circuit (IC) testing and in particular to testing ICs having scan chains using Level Sensitive Scan Design (LSSD).
BACKGROUND INFORMATION
Very Large Scale Integrated (VLSI) circuit devices have used serial scanning of flip-flops or latches for quite some time to set and observe the internal latch logic values for test and diagnostic purposes. Level sensitive scan design (LSSD) is an accepted test method used for manufacturing wafer test, logic built-in self-test, debug, and diagnostic testing.
FIG. 6
illustrates a prior art LSSD circuit configuration for LSSD latches. The LSSD latches have two modes of operation; in the first mode, the normal latch function is retained with a latch input, latch clock and latch output, and in the second mode, shift data is set into the latch and the result is shifted out via an output of a shift latch. In this way the normal latch output is used internally and the result of the scan input can be scanned out serially as in a shift register.
FIG. 7
is a circuit diagram illustrating a group of LSSD latches
701
,
702
, and
703
linked together where data is serially scanned into (scan_input
707
) and scanned out (scan_output
706
).
FIG. 8
also illustrates logic blocks
801
-
804
within a chip linked together with scan chains to allow larger blocks of logic to be tested.
Given the increasing complexities of the VLSI designs, LSSD techniques have become increasingly relied upon to solve time-to-market and manufacturing quality issues. At the same time, the wiring overhead to implement the scan chain connectivity increasingly interferes with achieving the marketable function (what the logic was designed to do) of the IC. The number of individual logic units and therefore the number of scan chains necessary to test the logic of the units has dramatically increased.
To facilitate the various testing modes that are possible with LSSD techniques, designs have used scan switches which are units that couple data from external sources to scan chains in different logic units within a VLSI chip. A source of LSSD data external to a chip must be coupled and directed to the various logic units that are to be tested inside the VLSI chip. While it is possible to construct large scan chains of LSSD latches for a logic unit, this connectivity is not efficient from a test time and test cost perspective. LSSD latches within a logic unit may be partitioned into smaller scan chains so data can be inputted to the scan chains in parallel for certain tests. If it is necessary to exercise a larger portion of the logic in a logic unit, then scan chains may be concatenated to facilitate this system level testing. A scan switch with connectivity to the various inputs and outputs of scan chains within logic units incorporates the functionality of scan chain concatenation. Because the data patterns necessary for the scan chains are complex, various linear feedback shift registers have been constructed for data generation within a scan switch. These data generators may cycle through large numbers of test cases which must be analyzed for logic faults. For this reason, methods using Multiple Input Shift Registers (MISR) are also employed in scan switches to enable signature analysis to increase test coverage and reduce test time.
LSSD methods have been key to enabling complex VLSI chips to be tested economically. However, coupling the many required scan chains has lead to heavy wiring congestion in the wiring channels normally reserved for creating the marketable logic functions of a chip. Therefore there is a need for a method to enable the various LSSD test modes required for VLSI chips while reducing the wiring complexity necessary to implement the test modes from a central scan switch.
SUMMARY OF THE INVENTION
Embodiments of the present invention partition the functionality of a single central scan switch into small globally distributed scan blocks to alleviate the unacceptable massive global wiring congestion created by the prior art designs. The small globally distributed scan blocks are designed with the functionality to generate scan data, provide concatenation of local scan chains, and generate signature patterns while requiring a minimum of control signals from a central location. To keep each scan block a minimum size, the logic circuitry necessary to generate the large test patterns and resulting signature patterns for logic built in self-test (LBIST) has also been partitioned so multiple scan blocks are necessary to generate a complete LBIST unit. A pseudo random pattern generator (PRPG) and a multiple input shift register (MISR) have been partitioned to minimize the size of the scan blocks. The scan blocks, therefore, may be placed in areas around logic units which may be too small for functional logic. Multiple scan blocks are wired to various logic units to allow concatenation of scan chains for LBIST, level sensitive scan design (LSSD) test and SYSTEM test. A number of scan blocks are also wired to generate a complete MISR and PRPG for the IC.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


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