Generation of test vectors for testing electronic circuits...

Details Generation of test vectors for testing electronic circuits... Generation of test vectors for testing electronic circuits...

2007-09-04

2007-09-04

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

10992922

ABSTRACT:
A method for generating test pattern signals weighted by the fault probability to greatly simplify the test process and to reduce the number of test vectors required for conducting the integrated circuit functionality tests. The method takes into consideration that the electrical short conditions occur mostly between adjacent nodes. The “fault coverage” concept is revised to test faults occurred between adjacent nodes and the test vectors are generated based a fault-probability weighted algorithm such that tests are conducted mostly on connections between adjacent nodes either on a same horizontal layer of between vertical nodes having vertical overlapping areas.

REFERENCES:
patent: 5414716 (1995-05-01), Bershteyn
patent: 6567946 (2003-05-01), Nozuyama
patent: 6728910 (2004-04-01), Huang
patent: 6920621 (2005-07-01), Toutounchi et al.
patent: 2005/0240887 (2005-10-01), Rajski et al.

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