Generator/compactor scan circuit low power adapter

Details Generator/compactor scan circuit low power adapter Generator/compactor scan circuit low power adapter

2011-04-12

2011-04-12

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

07925945

ABSTRACT:
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator102, compactor106, and controller110remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path502, to insert scan paths A506, B508and C510, and the insertion of an adaptor circuit504in the control path114between controller110and scan path502.

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“Two techniques for minimizing power dissipation in scan circuitsduring test application” by Chakravarty This paper appears in: Test Symposium, 1994., Proceedings of the Third Asian Publication Date: Nov. 15-17, 1994 on pp. 324-329 ISBN: 0-8186-6690-0 INSPEC Accession Number: 4868998.

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