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Evaluation device of weighted fault coverage and evaluation...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Evaluation of interconnect reliability using propagation...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Event based fault diagnosis

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Event based semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Event based test method for debugging timing related...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Event based test system storing pin calibration data in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Event phase modulator for integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Event processing apparatus and method for high speed event...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Event tester architecture for mixed signal testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Expectation based event verification

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Extending test sequences to accepting states

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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External scan circuitry connected to leads extending from...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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External trigger delay compensation apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Externally-loaded weighted random test pattern compression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Fabrication of test logic for level sensitive scan on a circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Fail array memory control circuit with selective input disable

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Failure analysis and testing of semi-conductor devices using...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Failure analysis and testing of semi-conductor devices using...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Failure analysis and testing of semi-conductor devices using...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Failure analysis device for IC tester and memory device measurin

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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