Fabrication of test logic for level sensitive scan on a circuit

Details Fabrication of test logic for level sensitive scan on a circuit Fabrication of test logic for level sensitive scan on a circuit

1998-02-10

2000-07-18

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714726, 714729, G01R 3128

Patent

active

060922265

ABSTRACT:
An input cell to the core logic on an electrical component and an output cell from the core logic on an electrical component are provided with a first signal path for data, a second signal path for scan data, a flip flop positioned near the pad of the core logic for selecting between said first signal path for data and second signal path for scan data. The scan data is used to input special signals or vectors to the core logic and to read the results of the scan data after it has passed through the core data and has been manipulated thereby. Several of the electrical components can be electrically connected to one another. The output cell of a first chip is electrically attached to the input cell of a second electrical component. The individual electrical components are connected on a printed circuit board and typically there are electrical conductors associated with the printed circuit board that are used to electrically connect the first chip or electrical component and the second chip or electrical component.

REFERENCES:
patent: 4875003 (1989-10-01), Burke
patent: 5017813 (1991-05-01), Galbraith et al.
patent: 5130988 (1992-07-01), Wilcox et al.
patent: 5621740 (1997-04-01), Kamada
patent: 5661407 (1997-08-01), Shibata
patent: 5677914 (1997-10-01), Fulcomer et al.

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