Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-04-12
2003-05-20
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S763010, C324S765010, C702S117000, C365S201000
Reexamination Certificate
active
06567941
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor devices such as ICs, and more particularly, to an event based semiconductor test system which stores calibration data concerning various parameters affecting test accuracy with respect to each pin unit in a non-volatile memory within the pin card.
BACKGROUND OF THE INVENTION
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals or test patterns produced by an IC tester at its appropriate tester pins at predetermined test timings. The IC tester receives output signals from the IC device under test in response to the test signals. The output signals are strobed or sampled by strobe signals at predetermined timings to be compared with expected output data to determine whether the IC device functions correctly.
The test signals are transmitted to the device under test through drivers which establish intended amplitude, impedance and slew rate of the test signals. The output response signals from the device under test are sampled by analog comparators by the timings of the strobe signals to be compared with predetermined threshold voltages. Both the drivers and analog comparators are typically assembled in a block called a pin electronics. Since the pin electronics involves analog values of the test signals and response signals as well as DC voltages and currents for DC parametric measurement, parameters in the pin electronics need to be calibrated to insure accurate measurement. This invention is directed to storage of such calibration data in the semiconductor test system.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based test system. Another type of test system is called an event based test system wherein the desired test signals and strobe signals are produced by event data from an event memory directly on a per pin basis. The present invention is better suited to such an event based semiconductor test system, although the present invention is also applicable to the traditional cycle based semiconductor test system having a per-pin architecture.
In an event based test system, notion of events are employed, which are any changes of the logic state in signals to be used for testing a semiconductor device under test. For example, such changes are rising and falling edges of test signals or timing edges of strobe signals. The timings of the events are defined with respect to a time length from a reference time point. Typically, such a reference time point is a timing of the previous event. Alternatively, such a reference time point is a fixed start time common to all of the events.
In an event based test system, since the timing data in a timing memory (event memory) does not need to include complicated information regarding waveform, vector, delay and etc. at each and every test cycle, the description of the timing data can be dramatically simplified. In the event based test system, as noted above, typically, the timing (event) data for each event stored in an event memory is expressed by a time difference between the current event and the last event. Typically, such a time difference between the adjacent events (delta time) is small, unlike a time difference from a fixed start point (absolute time), a size of the data in the memory can also be small, resulting in the reduction of the memory capacity.
As noted above, the pin electronics circuits in the semiconductor test system need the calibration for achieving accurate measurement of the device parameters. An example of types of calibration data that may be needed in a semiconductor test system includes (1) compensation of reference driving voltage, (2) compensation of reference comparison (threshold) voltage, (3) compensation of driving current load, (4) compensation of parametric (DC voltage and current) measurement circuits connected to the test pin, (5) compensation of timing strobes used to trigger comparisons, and (6) compensation of timing triggers used to drive test pin stimulus (test signals). There are other error factors which also affect accuracy and resolution of the test result. Such other error factors include signal propagation delay times in a performance board and a pin fixture provided between the pin cards and the device under test.
Therefore, there is a need to establish an effective way to maintain calibration data in the test system so that the compensation of various parameters can be conducted at a certain time interval or at each power up.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a semiconductor test system having a plurality of pin cards in which calibration data is stored in a pin card where each pin card includes a plurality of pin units where each pin unit is configured as an event based tester.
It is another object of the present invention to provide a semiconductor test system wherein each pin card having a plurality of pin units therein includes a non-volatile memory to store the calibration data of various parameters involved in the pin units in the pin card.
It is a further object of the present invention to provide an event based semiconductor test system wherein each pin card having a plurality of pin units therein includes a non-volatile memory for storing the calibration data of various parameters involved in the pin units and a processor for conducting a calibration process of the pin card.
It is a further object of the present invention to provide an event based semiconductor test system which has a cost effective, error free, secure and simple way of managing the calibration data for all of the pin cards used therein.
The present invention is a semiconductor test system for testing an electronics device under test (DUT) by producing events of various timings for supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The timings of the events can be freely changed by changing the timing data in an event memory.
In the present invention, the semiconductor test system is comprised of a large number of test channels for testing a semiconductor device under test (DUT) by applying test patterns to device pins of the DUT through the test channels and examining response outputs of the DUT. The test system is comprised of a plurality of pin cards each having a, plurality of pin units therein to establish a part of the test channels, a non-volatile memory provided within each pin card for storing calibration data for compensating error factors involved in the pin units mounted in the corresponding pin card, and a microprocessor provided within each pin card for managing the calibration data and executing the calibration procedure for all of the pin units in the corresponding pin card, where each pin unit is configured as an event tester in which a test pattern or a strobe signal is directly generated based on event data stored in an event memory which defines any changes from a previous event with reference to a time difference therefrom.
The calibration data includes data for compensating error factors regarding parameters used in the corresponding pin card in testing the DUT. For example, the calibration data includes data for compensating error factors including timings and reference voltages of the test patterns, timings of strobe signals and reference comparison voltages.
In a further aspect, the event based test system of the present invention further includes a performance board unique to the DUT for mounting the DUT thereon and having signal paths for transmitting signals to and from the DUT, and a pin fixture for interconnecting the plurality of pin cards in the test system with the performance board. In such a configuration, it is preferable that the calibration data includes data for compensating error factors includin
Rajsuman Rochit
Sugamori Shigeru
Turnquist James Alan
Advantest Corp.
Britt Cynthia
De'cady Albert
Muramatsu & Associates
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