Failure analysis and testing of semi-conductor devices using...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S741000, C703S013000

Reexamination Certificate

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11670031

ABSTRACT:
The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.

REFERENCES:
patent: 5233337 (1993-08-01), Takahashi
patent: 6128754 (2000-10-01), Graeve et al.
patent: 6658604 (2003-12-01), Corbin et al.

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