Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-04-30
2001-08-21
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S073100
Reexamination Certificate
active
06279130
ABSTRACT:
FIELD THE INVENTION
The subject invention concerns the field of test and measurement equipment in general, and triggering apparatus for such test and measurement equipment in particular.
BACKGROUND OF THE INVENTION
It is quite common when troubleshooting an electronics unit to employ multiple pieces of test equipment simultaneously in an effort to identify the cause of faulty operation of the electronics unit. In this regard, it is often advantageous for a user to trigger one test and measurement instrument from another (or from an external source). For example, a user may want to use a TRIGGER OUT signal from a logic analyzer to trigger an oscilloscope. In this way, the user can set up the logic analyzer to capture a series of data words upon the occurrence of a particular binary word, and also produce the TRIGGER OUT signal to cause an oscilloscope to acquire a waveform related in time to the captured logic analyzer data record.
In sharp contrast to the simple example given above, modern logic analyzers have powerful multistate triggering capability that provides triggering on a particular sequence of events leading to a fault.
Unfortunately, a problem arises in that the generation of the TRIGGER OUT signal from the logic analyzer is delayed in time by a significant amount due to the time required for internal processing of the triggering event. This causes the oscilloscope to trigger at a delayed trigger point rather than at the earlier desired point in time coinciding with the triggering event.
It is known to apply a test signal with an unambiguous trigger event therein simultaneously to both the logic analyzer and the oscilloscope, for the purpose of determining the length of the TRIGGER OUT signal delay. After having determined the value of the internal delay, (and any additional delay caused by the length of the TRIGGER OUT signal cable), the user can compensate by searching backward through the stored oscilloscope waveform images to a point displaced from the actual trigger point by a time period equal to the delay period.
Currently, in order to actually accomplish this task, a user must calculate the location of the point in waveform memory at which the desired trigger should have occurred. It should be noted that the calculations performed are only valid for a given time base setting. If the user adjusts the oscilloscope time base controls, then the calculations must be performed again
Most importantly, it should also be understood that when the desired point in memory is reached (usually by rotating a dial or knob to search through memory), there is no visual indication (i.e., marker) displayed on-screen to identify the desired point to the user. Thus there is a certain amount of uncertainty for the user, that the task of searching through memory to locate a specific point (i.e., the trigger event point) was successfully accomplished.
Unfortunately, the oscilloscope has no way of knowing that it has been triggered by a delayed TRIGGER OUT signal. Thus, it is not currently possible for an oscilloscope to display the data acquired at the desired trigger point, because the oscilloscope does not receive the necessary information that would allow it to calculate and generate this marker.
SUMMARY OF THE INVENTION
A Trigger delay compensation apparatus for use in a digital storage oscilloscope, includes a trigger circuit for receiving a TRIGGER OUT signal generated from a logic analyzer in response to a logic analyzer trigger event signal, for starting a post trigger counter. It also includes a data entry circuitry for entering data input by a user, the data being representative of a delay between a reception of the logic analyzer trigger event signal and the generation of the TRIGGER OUT signal by the logic analyzer. A post trigger counter stops an acquisition of signal data upon expiration of a count of the post trigger counter. A controller, coupled to the data entry circuitry and to the post trigger counter receives the delay representative data, and adjusts the count of the post trigger counter in a direction to compensate for the delay. The compensation delay allows display circuitry to display a portion of the acquisition that is centered about the logic analyzer trigger event, rather than the DSO trigger event.
REFERENCES:
patent: 4730314 (1988-03-01), Noguchi
patent: 4972138 (1990-11-01), Bush
patent: 5001714 (1991-03-01), Stark et al.
Chung Phung M.
Lenihan Thomas F.
Tektronix Inc.
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