Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-03-22
2003-05-20
Chung, Phung M (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06567946
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-077428, filed Mar. 23, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a fault coverage evaluation device of a logic circuit and an evaluation method thereof, and more particularly to testing technology of logic LSI, VLSI and the like, fault grading technology including fault simulation technology, and technology for enhancing quality of manufacturing products.
In a prior art of fault coverage evaluation device and evaluation method, proper faults are assumed in inner nodes in an LSI or its inner logic circuit, it is calculated how many faults can be detected by test patterns for testing operation of the LSI by employing the fault simulation technology, and the fault coverage of the test patterns is evaluated.
In particular, the fault simulation in which a stuck-at fault being the inner node fixed at 0 or 1 is an assumed fault is relatively easy in calculation, and it is known that the obtained fault coverage has a strong correlation with the rate of defective LSI chips mixed in those judged as good (defect free) after selection by using the test patterns, or the defective chip rate occurring in the market after shipping of LSI chips.
Therefore, if the fault coverage of test patterns is low, a high fault coverage may be achieved by adding or improving the test patterns, so that the shipping quality of LSI may be enhanced somewhat. However, since this correlation is not always strict, a very high fault coverage is demanded if a sufficiently high manufacturing quality is desired to be maintained.
On the other hand, the test patterns are generally added or improved manually on the basis of the experience, and in order to achieve a certain high fault coverage, a very long period is needed, and to obtain a sufficiently high manufacturing quality, a more advanced testability design method must be employed.
In the testability design method, however, the test patterns were hitherto generated automatically by, for example, an ATPG (automatic test pattern generator), and by using them, or by using test patterns improved by adding them to the original test patterns, the LSI and its inner logic circuit was tested, but the principle was a method of evaluating the fault coverage of the test patterns by assuming the faults stuck-at “0” or “1” commonly in inner nodes, and it requires much more additional circuits for testing or an enormous CPU time in order to obtain a fault coverage above a certain level, and in spite of such immense cost, sometimes sufficiently high manufacturing quality could not be achieved.
In the conventional evaluation of fault coverage, the reason why the correlation is not expected above a certain level will be explained below. In an actual LSI, portions corresponding to logic connection nodes for mutually connecting input and output terminals of the internal basic cells, and input terminal and output terminal of internal basic cells (hereafter called logic connection nodes unless otherwise specified, and such input terminal and output terminal including bidirectional terminal) are widely varied, including those having short wiring or long wiring in layout, having many connecting portions composed of a single contact, more specifically a single minimum-size contact, and not containing such connecting portions at all.
Herein, a basic cell refers to a logic circuit performing a basic logic operation, including a single device as a minimum unit and the one performing relatively complicated logic operation.
On the other hand, in a premature process, until stabilized at a level of high yield, faults of specific modes may occur frequently, such as open fault of contact and short-circuit fault. In such circumstance, therefore, the actual fault occurrence rate differs in each logic connection node.
In the conventional fault simulation, however, faults stuck at either “0” or “1” only were assumed for each logic connection node, and the fault coverage was determined only in terms of rate of detection of faults by predetermined test patterns.
Accordingly, in the conventional fault simulation, it was extremely difficult to point out problems in the manufacturing process by comparing the results of tests of an LSI fabricated by the manufacturing process and the fault simulation result of the LSI, in a sense that which mode of fault is most likely to occur.
As clear from the description herein, moreover, in the existing fault simulation, basically, in logic connection nodes of the LSI, only two faults stuck at 0 and 1 are assumed commonly, it cannot cope with problems that the fault occurrence rate varies in each logic connection mode when the manufacturing process or the shape of layout pattern differs.
If the manufacturing process or the shape of layout pattern differs, however, it is highly possible that the fault occurrence rate varies in the logic connection nodes, and in the conventional fault simulation, it was completely ignored that the amount of layout related parameter information closely related to the occurrence of fault fluctuates in each logic connection node.
Herein, the layout related parameter information is the constituting elements of layout data to be extracted in relation to the fault assumed in the logic connection nodes of notice, from the layout information of the objective LSI, and the constraints and rules for determining such elements.
More specifically, the layout related parameter information includes layout information related to the occurrence rate of faults, for example, the length of wiring, number of connecting portions composed of a single minimum-size contact.
The amount of layout related parameter information is the amount or value determined according to the information on the layout, and it is the basis for determining the weighting amount relative to occurrence of fault given to each logic connection node of notice. The amount of layout related parameter information is more specifically described in the embodiments of the present invention.
Thus, in the conventional fault simulation, since no consideration was given to the correspondence between the fault assumed in each logic connection node and the portion likely to cause fault actually in layout, in order to improve the manufacturing quality of LSI, the test pattern designer was forced to add test patterns only for the purpose of achieving an assigned level of fault coverage, and in spite of an tremendous resource investment, substantially, it was difficult to prepare test patterns of high quality timely at the early stage of mass production when effects of high fault coverage are most likely to be obtained.
BRIEF SUMMARY OF THE INVENTION
As described above, in the conventional fault coverage evaluation device and evaluation method, since consideration was not given to the correspondence between the fault assumed in each logic connection node and the portion likely to cause fault actually in layout, despite an tremendous resource investment, there was a problem that test patterns of high quality could not be prepared.
The present invention is devised in order to solve these problems, and it is hence an object thereof to provide an evaluation device of weighted fault coverage and an evaluation method thereof capable of preparing test patterns of high quality in a short period by a small resource investment, and greatly contributing to improvement of manufacturing quality of LSI at the early stage of mass production when effects of high fault coverage are likely to appear, by setting up correspondence between the amount of layout related parameter information closely relating to occurrence of fault and the logic connection nodes.
In the evaluation device and evaluation method of weighted fault coverage of the present invention, in a large scale integration (LSI) such as system LSI, in order to feed back the result of fault simulation to quality improve
Chung Phung M
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
Evaluation device of weighted fault coverage and evaluation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Evaluation device of weighted fault coverage and evaluation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Evaluation device of weighted fault coverage and evaluation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3072308