Event based test method for debugging timing related...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S700000

Reexamination Certificate

active

10412078

ABSTRACT:
A test method for debugging failures of an IC device with use of an event based semiconductor test system is capable of distinguishing a timing related failure from other failures. The test method includes the steps of: applying a test signal to a DUT and evaluating a response output of the DUT, detecting a failure in the response output, identifying a reference clock signal related to the failure, identifying a portion of the reference clock signal that is directly related to the failure, and incrementally changing a timing of events for the identified portion of the reference clock signal to detect change in the response output from the DUT.

REFERENCES:
patent: 5592659 (1997-01-01), Toyama et al.
patent: 6331770 (2001-12-01), Sugamori
patent: 6377065 (2002-04-01), Le et al.
patent: 6401225 (2002-06-01), Miura
patent: 6785858 (2004-08-01), Niiro

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