Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-03-31
2002-06-11
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000
Reexamination Certificate
active
06405333
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly a fail array memory control circuit with a selective input disable apparatus for use in a semiconductor tester to test semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor device fabrication involves numerous complex processes that include not only actual fabrication steps, but also verification steps to ensure the acceptability of the fabrication steps. One of the more important verification processes includes testing each device with automatic test equipment to verify operability according to expected electrical parameters. The testing is usually carried out at both the wafer and packaged-device levels to maximize wafer yields.
Automatic test equipment, individually referred to as a tester, comprises a sophisticated computer-controlled system that generally stimulates selected pins of a device-under-test (DUT) with input signals, or vectors, and captures the responsive DUT outputs for comparison to expected DUT outputs. The capture and comparison is generally carried out by failure analysis circuitry. If the captured signals match the expected signals under various conditions, the DUT continues through the fabrication process. Should the comparison identify inconsistent results, the tester processes information concerning the fault in the failure analysis circuitry for subsequent evaluation by the semiconductor manufacturer. In circumstances where consistent failures in multiple DUTs are observed, the failure analysis becomes critically important in determining why the failures are being caused.
Conventional failure analysis circuitry in a tester typically includes several data storage elements for storing failure-related data. One such element comprises a failure capture memory, or catchram, that stores fail information in address locations corresponding to the address locations of a failed memory cell in the DUT. The catchram allows the tester to provide a bit image representation of the failed DUT. Information relating to the individual failures, such as the pattern state, and the address and data bits associated with the failed memory cell location, are stored in a memory element often referred to as the fail vector memory (FVM) or history RAM.
Conventional FVM's are typically fairly wide in order to store the entire state of the machine, but have a relatively small overall storage capacity, anywhere from about 256 to 1024 locations deep. Failures detected from the individual pins of the DUT are processed as sync-reject signals, and ORed to form a failure control signal bitstream. The bitstream feeds an FVM controller that issues write commands to the FVM for each sync-reject signal received.
In response to the FVM controller, the FVM loads into each location in the memory information associated with each individual failure. The information is received from data source inputs regarding a particular cycle of pattern information relating to an individual failure, such as subroutine vector address, subroutine vector accumulator value, cycle counter value, and as noted above, address and data bits. With such information, a subsequent evaluation of a DUT failure is relatively straightforward. One example of a failure analysis circuit consistent with the above description is found in the Marlin Memory Tester, manufactured by Teradyne, Inc., Agoura Hills, Calif.
One of the problems that conventional FVM configurations often encounter involves unexpected large streams of failures resulting from faulty sync-reject channels, or a large number of failures occurring due to high performance testing. In such circumstances, conventional FVM circuits often become overwhelmed by the data, causing the memory to fill quickly and in some circumstances, wrap around. This often results in an undesirable loss of failure analysis data.
What is needed and heretofore unavailable is a failure vector memory circuit for use in a semiconductor tester that selectively disables individual channels to prevent the FVM from prematurely filling. The fail capture memory circuit of the present invention satisfies this need.
SUMMARY OF THE INVENTION
The fail array memory control circuit of the present invention provides a selective disable feature per device-under-test (DUT) pin that prevents a per-pin failure vector memory (FVM) from prematurely reaching capacity. As a result, more accurate failure data is retained concerning failures detected during a test while minimizing any loss of DUT failure data.
To realize the foregoing advantages, the invention in one form comprises a memory control circuit for use in a data path of a failure capture circuit to selectively control the storage of failure information associated with a pin of a device-under-test. The memory control circuit includes a memory controller operative to generate a store signal in response to a failure control signal and a semiconductor memory having a control input coupled to the controller for receiving the store signal. The memory controller operates in response to the store signal to write failure information associated with a particular failure control signal. Disable logic in the memory control circuit is operative according to predetermined conditions for selectively inhibiting the delivery of the failure control signals to the memory controller.
In another form, the invention comprises a failure capture circuit for use in a semiconductor tester for capturing and processing output signals generated by a device-under-test. The failure capture circuit includes capture logic for capturing output pin data from the device-under-test and fail array logic for processing the output pin data. The fail array logic includes a plurality of channels corresponding to the DUT pins. Each channel includes failure detection logic for identifying failures in the captured pin data and generating failure signals representing the identified failures. Per-pin memory is provided in the fail array logic for storing failure information associated with the identified failures and includes a control signal input. The fail array logic also includes disable logic coupled to the failure detection logic for selectively inhibiting propagation of the failure signals. A memory controller is coupled to the disable logic for generating store command signals to the memory control signal input in response to receiving failure signals selectively passed by the disable logic.
In a further form, the invention comprises a method of controlling the storage of failure information in a failure vector memory controlled by a memory controller responsive to failure control signals. The method includes the steps of: identifying failures relating to a pin of a device-under-test; generating failure control signals indicative of the detected failures; routing the failure control signals to the memory controller; and selectively disabling the routing step when the number of failure control signals reaches a predetermined level.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
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Teradyne Marlin Memory Tester Digital Block Diagram dated Nov. 1994, channel card portion.
Kreisman Lance M.
Teradyne, Inc.
Ton David
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