LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling,Digital logic testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Distributed test control architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Divided scan path with decode logic receiving select control...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Domino scan architecture and domino scan flip-flop for the testi

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

DRAM stacked package, DIMM, and semiconductor manufacturing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Driver for integrated circuit chip tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Driver IC and inspection method for driver IC and output device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dual controllers for scan paths, distributors, and collectors

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dual mode memory for IC terminals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dual mode memory for IC terminals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dual mode test access port method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dual scan chain design method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dual site loadboard tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Duty cycle characterization and adjustment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Duty cycle characterization and adjustment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

DVI link with parallel test data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

DVI link with parallel test data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dynamic logic element having non-invasive scan chain insertion

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dynamic logic scan gate method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Dynamic scan chains and test pattern generation...