Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-06-13
2006-06-13
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
07062692
ABSTRACT:
Method and apparatus are described for duty cycle determination and adjustment. More particularly, an output signal is sampled and provided to duty cycle check circuitry which characterizes the duty cycle of the sampled output signal. This characterization may be provided to a wafer prober or integrated circuit tester to determine whether duty cycle is within an acceptance range. Alternatively, the duty cycle indicator signal may be provided to drive adjustment circuitry. In response to duty cycle not being within an acceptance range, drive adjust circuitry provides a drive adjustment signal to adjust duty cycle at an output buffer by turning on one or more p-channel drive transistors, one or more n-channel drive transistors, or a combination of both. Moreover, wells may be biased responsive to a detected duty cycle in order to correct the duty cycle.
REFERENCES:
patent: 5256916 (1993-10-01), Thurston
patent: 6219305 (2001-04-01), Patrie et al.
patent: 6324485 (2001-11-01), Ellis
patent: 6687865 (2004-02-01), Dervisoglu et al.
patent: 2002/0079940 (2002-06-01), Boerstler et al.
De'cady Albert
Gandhi Dipakkumar
Maunu LeRoy D.
Webostad W. Eric
Xilinx , Inc.
LandOfFree
Duty cycle characterization and adjustment does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Duty cycle characterization and adjustment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Duty cycle characterization and adjustment will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3636542