Distributed test compression for integrated circuits

Details Distributed test compression for integrated circuits Distributed test compression for integrated circuits

2011-07-12

2011-07-12

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07979764

ABSTRACT:
A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.

REFERENCES:
patent: 6611933 (2003-08-01), Koenemann et al.
patent: 7032148 (2006-04-01), Wang et al.
patent: 7197721 (2007-03-01), Patil et al.
patent: 7512851 (2009-03-01), Wang et al.
IEEE Computer Society,“IEEE Standard Testability Method for Embedded Core-based Integrated Circuits,” IEEE Standards Board, 1500-2005, IEEE Publication, USA, 2005.
Barnhart, C., et al. “OPMISR: The Foundation for Compressed ATPG Vectors,” Proc. International Test Conference, pp. 748-757, 2001.
Barnhart, C., et al. “Extending OPMISR Beyond 10x Scan Test Efficiency,” Design & Test of Computers, IEEE, pp. 65-73, Sep.-Oct. 2002.
Koenemann, B., et al., “A SmartBlST Variant with Guaranteed Encoding,” Proc. Asian Test Symposium, pp. 325-330, 2001.
IEEE Computer Society, “IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data-Core Test Language (CTL),” IEEE Standards Board, 1450.6-2005, IEEE Publication, USA, 2005.
Orailoglu, B., et al., “Test Volume and Application Time Reduction Through Scan Chain Concealment,” Proc. Design Automation Conference., pp. 151-161, 2001.
Lee, K., et al., “Using a Single Input to Support Multiple Scan Chains,” Proc. of the International Conference on Computer-Aided Design, pp. 74-78, Nov. 1998.
Hamzaoglu, I., et al., “Reducing Test Application Time for Full-Scan Embedded Cores,” Digest of Papers, 29th International Symposium on Fault-Tolerant Computing, pp. 260-267, Jun. 1999.
Hsu, F., et al., “A Case Study on the Implementation of the Illinois Scan Architecture,” Proc. International Test Conference, pp. 538-547, 2001.
Rajski, J. et al., “Embedded Deterministic Test for Low-Cost Manufacturing Test,” Proc. International Test Conference, pp. 301-310, 2002.
Mitra, K. S., et al., 'X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction, pp. 311-320, 2002.
Wohl, J.A., et al., “X-Tolerant Compression and Application of Scan-ATPG patterns in a BIST architecture,” Proc. International Test Conference, pp. 727-736, 2003.
Keller, B., et al., “An Economic Analysis and ROI Model for Nanometer Test,” Proc. International Test Conference, 2004.
Gallagher, P., et al. “A Building Block BIST Methodology for SoC Designs: A Case Study,” Proc. International Test Conference, pp. 111-120, 2001.
Keller, B., et al., “Built-In Self-Test Support in the IBM Engineering Design System,” IBM Journal of Research and Development, pp. 405-415, Mar. 1990.
Paul H. Bardell and William H. McAnney, “Self-Testing of Multi-Chip Logic Modules,” Reprinted from Proceedings International Test Conference, pp. 200-204, 1982.

Affiliated with

Also associated with

Rating

Distributed test compression for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Distributed test compression for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Distributed test compression for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2727774