Dual scan chain design method and apparatus

Details Dual scan chain design method and apparatus Dual scan chain design method and apparatus

2003-11-19

2010-02-02

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S731000

Reexamination Certificate

active

07657809

ABSTRACT:
A method for testing an integrated circuit includes scanning test data from an input and an output pin into a first scan chain during a first state of a clock cycle, and scanning test data from the same input and output pins into a second scan chain during a second state of the clock cycle.

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