DRAM stacked package, DIMM, and semiconductor manufacturing...

Details DRAM stacked package, DIMM, and semiconductor manufacturing... DRAM stacked package, DIMM, and semiconductor manufacturing...

2006-03-20

2009-06-09

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

07546506

ABSTRACT:
The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

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Search Report in Taiwanese Patent Application No. 095107071 mailed Apr. 27, 2009. (No English translation).

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