Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-01-15
2000-05-30
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3728
Patent
active
060702591
ABSTRACT:
A scannable dynamic logic element includes a clock input, a test enable input, a data output, a precharge circuit, a boolean pull-down circuit and a test scan pull-down circuit. The precharge circuit is coupled between a first supply terminal and the data output and has a precharge control input coupled to the clock input. The boolean pull-down circuit is coupled between the data output and the second supply terminal and has a logic data input, a first evaluation control input which is coupled to the clock input and a first enable input which is coupled to the test enable input. The test scan pull-down circuit is coupled between the data output and the second supply terminal and has a test data input, a second evaluation control input which is coupled to the clock input and a second enable input which is coupled to the test enable input.
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Grover David B.
Roisen Roger
Cady Albert De
Greene Jason
LSI Logic Corporation
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