Dual mode memory for IC terminals

Details Dual mode memory for IC terminals Dual mode memory for IC terminals

1996-11-15

1999-08-17

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

365201, G01R 3128

Patent

active

059387831

ABSTRACT:
An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal thereof, which signal path includes a memory circuit (121C, 127C). The memory circuit is coupled to the output terminal and is selectively operable to detect and resolve voltage contention at the output terminal, and is also selectively operable to isolate itself from voltages at the output terminal.

REFERENCES:
patent: 5134314 (1992-07-01), Wehrmacher
patent: 5701307 (1997-12-01), Whetsel
patent: 5715255 (1998-02-01), Whetsel
Bulent Dervisoglu, "IEEE P1149.2 Description and Status Report", IEEE, Sep. 1992, pp. 79-81.
L. Whetsel, "IEEE STD. 1149.1-An Introduction", Nepcon, Feb. 1993, 10 pages.
Unapproved Draft IEEE P1149.2-D2.5, "Extended Digital Serial Subset", IEEE, Aug. 1994, pp. 1-37.
Dilip K. Bhavsar, "Chapter 17. Cell Designs that Help Test Interconnect Shorts," IEEE, 1990 pp. 183-189.
David George, "Use a Reprogrammable Approach to Boundary Scan for FPGAs", EDN Electrical Design News, vol. 38, No. 16, Aug. 5, 1993, pp. 97-100.

Affiliated with

Also associated with

Rating

Dual mode memory for IC terminals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual mode memory for IC terminals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual mode memory for IC terminals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-311213