Duty cycle characterization and adjustment

Details Duty cycle characterization and adjustment Duty cycle characterization and adjustment

2003-03-27

2008-10-14

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C327S175000

Reexamination Certificate

active

07437633

ABSTRACT:
Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.

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U.S. Appl. No. 10/255,502, filed Sep. 26, 2002, Lesea.

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