LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling,Digital logic testing

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Circuit and method for fuse disposing in a semiconductor...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for increasing scan cell observability of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for integrated circuit configuration

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for performing built-in self test and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for testing a circuit having memory array...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Circuit and method for testing embedded phase-locked loop...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for testing physical layer functions of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method for testing semiconductor device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method providing dynamic scan chain partitioning

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and method to prevent inadvertent test mode entry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Circuit and method to prevent inadvertent test mode entry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Patent

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Circuit and method to prevent inadvertent test mode entry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit and/or method for automated use of unallocated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit apparatus and method for testing integrated circuits...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit arrangement and method for checking the function of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit arrangement and method for driving electronic chips

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Circuit arrangement and method for driving electronic chips

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

[ 0.00 ] – not rated yet Voters 0 Comments 0

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