Circuit arrangement and method for driving electronic chips

Details Circuit arrangement and method for driving electronic chips Circuit arrangement and method for driving electronic chips

2004-10-14

2008-09-16

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07426669

ABSTRACT:
The invention provides a method for testing circuit units to be tested in a test apparatus, different identification units being assigned to the circuit units to be tested, the circuit units to be tested being connected to the test apparatus, a tester data stream including command blocks being output from the test apparatus, the tester data stream being compared with the identification units, the circuit unit to be tested, the identification unit of which matches the tester data stream output by the test apparatus, being activated and at least one command block for this circuit unit to be tested being processed in the circuit unit to be tested, whereupon the circuit unit to be tested is deactivated.

REFERENCES:
patent: 6640323 (2003-10-01), Akram
patent: 7185255 (2007-02-01), Shibuya
patent: 7228474 (2007-06-01), Williams et al.
patent: 2005/0034043 (2005-02-01), Takizawa
patent: 199 37 820 (2000-03-01), None
patent: 1 212 629 (2004-11-01), None

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