Circuit and method to prevent inadvertent test mode entry

Details Circuit and method to prevent inadvertent test mode entry Circuit and method to prevent inadvertent test mode entry

1997-06-26

1999-08-31

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

059448458

ABSTRACT:
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

REFERENCES:
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patent: 5408435 (1995-04-01), McClure et al.
patent: 5475640 (1995-12-01), Kersh, III et al.
patent: 5604756 (1997-02-01), Kawata
patent: 5615164 (1997-03-01), Kirihata et al.
patent: 5831997 (1998-11-01), Kodashiro

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