Circuit and method for testing a circuit having memory array...

Details Circuit and method for testing a circuit having memory array... Circuit and method for testing a circuit having memory array...

2007-03-06

2007-03-06

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C365S201000

Reexamination Certificate

active

10889923

ABSTRACT:
A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that are output by the circuit under test with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.

REFERENCES:
patent: 5899961 (1999-05-01), Sundermann
patent: 6144595 (2000-11-01), Hirooka et al.
patent: 6154861 (2000-11-01), Harward
patent: 6178532 (2001-01-01), Pierce et al.
patent: 6484278 (2002-11-01), Merritt et al.
patent: 6536004 (2003-03-01), Pierce et al.

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