Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-07-24
2003-05-13
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S201000
Reexamination Certificate
active
06564351
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, in particular, to a circuit and method for testing an integrated circuit.
BACKGROUND OF THE INVENTION
An integrated circuit comprises a large number of semiconductor devices, such as transistors, that are fabricated on a semiconductor substrate. Integrated circuits are produced in quantity on fabrication lines. Before an integrated circuit is sold, the manufacturer tests the integrated circuit for defects so that corrective action can be taken, if possible. To test the integrated circuit, the manufacturer applies test signals to selected pins of the integrated circuit. To speed up the process of testing large integrated circuits such as memory devices, the signals used to test the integrated circuit differ from the signals used in normal operation, even though the signals in both modes use the same pins of the integrated circuit. Therefore, designers have developed various techniques to differentiate test and normal modes of operation. Because this test mode should not be used once the chip successfully completes the tests, precautions must be taken to assure that the ultimate user of the integrated circuit cannot inadvertently activate the test mode.
In a typical dynamic random access memory (DRAM) device, a voltage that is above the power supply voltage for the integrated circuit, referred to as a super-voltage, is applied to a pin to place the device into test mode. Once in test mode, the manufacturer can test the operation of the memory device. To exit test mode, the super-voltage is removed from the pin. By using the super-voltage to enter test mode, it is unlikely that an ed user will place the device in test mode inadvertently. As the size of integrated circuits gets smaller, the risk of damaging the integrated circuit due to dielectric and junction breakdown increases when a super-voltage is used.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a circuit and method for entering test mode that reduces the risk of damage to the integrated circuit.
SUMMARY OF THE INVENTION
The above mentioned problems with testing of integrated circuits and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A circuit and method for testing integrated circuits is described which enters test mode based on a pulse in a control signal wherein the pulse provides a voltage that exceeds a threshold voltage for a period of time that is less than the duration of the testing. Advantageously, the circuit and method thus allow testing of the integrated circuit with reduced risk of shorting out components of the circuit as the size of the integrated circuits gets smaller.
In particular, one illustrative embodiment of the present invention provides a test mode detector that places a multi-pin integrated circuit, such as a dynamic random access memory (DRAM), in test mode. The test mode detector comprises a pulse detector that receives a control signal. The control signal controls when the integrated circuit is in test mode. The test mode detector further includes a latch that is responsive to the pulse detector so as to set the latch when the pulse detector detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit in test mode for a period of time that is greater than the duration of the pulse of the control signal.
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Schwegman Lundberg Woessner & Kluth P.A.
Ton David
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