Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-01-23
2007-01-23
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C327S141000, C327S147000, C327S023000, C324S076580, C324S076610
Reexamination Certificate
active
10352439
ABSTRACT:
A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.
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The TTL Data Book vol. 2: Texas Instruments, 1985, TI, vol. 2, p. 3-518.
Chen Murphy
Hu Perlman
De'cady Albert
Radosevich Steven D.
VIA Technologies Inc.
Volpe and Koenig P.C.
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