Circuit and method for integrated circuit configuration

Details Circuit and method for integrated circuit configuration Circuit and method for integrated circuit configuration

2007-08-27

2010-12-14

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S741000, C714S745000, C702S085000

Reexamination Certificate

active

07853845

ABSTRACT:
An auto-trim circuit that sets trim bits for an integrated circuit includes a coarse bit calibration circuit for determining a first portion of the trim bits as a set of coarse bits, and a fine bit calibration circuit for determining a second portion of the trim bits as a set of fine bits wherein said fine bits.

REFERENCES:
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patent: 5651014 (1997-07-01), Kobayashi
patent: 6070256 (2000-05-01), Wu et al.
patent: 6338032 (2002-01-01), Chen
patent: 6667918 (2003-12-01), Leader et al.
patent: 6927624 (2005-08-01), Ivanov et al.
patent: 6993467 (2006-01-01), Gavrila et al.
patent: 2006/0276986 (2006-12-01), Anderson et al.

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