Circuit and method providing dynamic scan chain partitioning

Details Circuit and method providing dynamic scan chain partitioning Circuit and method providing dynamic scan chain partitioning

2011-05-03

2011-05-03

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S729000, C714S731000

Reexamination Certificate

active

07937634

ABSTRACT:
The circuit and method providing dynamic scan chain partitioning delivers peak power reduction by dynamically partitioning scan chains into multiple groups, wherein transitions are equally distributed among these multiple groups. For each test pattern, a particular partitioning that leads to the even partitioning of the transitions is computed by analyzing the transition distribution of the pattern. The scan chain partitioning is formulated using an Integer Linear Programming (ILP) and an efficient greedy heuristic. The computed information is loaded into the reconfigurable scan chain partitioning hardware during the capture window. The partitioning hardware is composed of controllable clock gating logic, which is reconfigured on a per pattern basis, wherein the reconfiguration is effected by only utilizing the existing scan channels. The reconfigurability delivers a solution that is test set independent. The results confirm the superiority of dynamic scan chain partitioning over static partitioning techniques in terms of peak power reduction.

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Myung-Hoon Yang ; Taejin Kim ; Yongjoon Kim ; Sungho Kang ; Segmented scan architecture using segment grouping for test cost reduction, Issue Date : Nov. 24-25, 2008, International SoC Design Conference, 2008. ISOCC '08.

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