Circuit and method for performing built-in self test and...

Details Circuit and method for performing built-in self test and... Circuit and method for performing built-in self test and...

2007-08-14

2007-08-14

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

11160102

ABSTRACT:
A circuit and a method for built-in self test (BIST) and a computer readable recording medium for storing program thereof are provided. The BIST circuit serves a system to self test a circuit-under-test in the system. The system further includes a unit circuit having a plurality of input terminal couple to a plurality of signal path respectively, and an output terminal couple to the circuit-under-test. A selection and activation circuit of the BIST circuit having an output terminal couple to one of input terminals of the unit circuit, one input terminal couple to a non-timing-critical path of the signal paths, and the other input terminal receives a test signal. When the system operates in a test mode, the BIST controller provides the test signal through the selection and activation circuit and the unit circuit to test the circuit-under-test.

REFERENCES:
patent: 4703484 (1987-10-01), Rolfe et al.
patent: 5854752 (1998-12-01), Agarwal
patent: 6148425 (2000-11-01), Bhawmik et al.
patent: 6289477 (2001-09-01), Gunadisastra
patent: 6541994 (2003-04-01), Masuda
patent: 6907555 (2005-06-01), Nomura et al.
patent: 6934205 (2005-08-01), Pandey et al.

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