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Test channel usage reduction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Test circuit and a redundancy circuit for an internal memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit and circuit test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit and method for DC testing LSI capable of preventing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Test circuit and method for hierarchical core

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit and method for interconnect testing of chips

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit and method for system logic

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit and system for interconnect testing of high-level p

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Test circuit and test method for testing semiconductor chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Test circuit capable of sequentially performing boundary...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit capable of testing embedded memory with...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit for exposing higher order speed paths

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit for logical integrated circuit and method for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit for semiconductor device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit for semiconductor integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit provided with built-in self test function

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit topology reconfiguration and utilization...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test circuit, integrated circuit, and test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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