Test circuit and method for DC testing LSI capable of preventing

Details Test circuit and method for DC testing LSI capable of preventing Test circuit and method for DC testing LSI capable of preventing

1998-03-09

2000-06-13

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060761784

ABSTRACT:
A test circuit for DC testing which has a simple layout design and never causes malfunction due to simultaneous change of outputs includes test circuits connected to inputs of output allowable buffers. The test circuits are connected in a circle so that a value retained in each circuit can be applied to the adjacent test circuit. In the DC testing using the test circuit for DC testing, values which are retained in and output from output allowable buffers are circulated between the output allowable buffers. At the time, the values retained in the test circuit are changed within the range of the number allowable for simultaneous change.

REFERENCES:
patent: 4825439 (1989-04-01), Sakashita et al.
patent: 5221865 (1993-06-01), Phillips et al.

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