Test circuit, integrated circuit, and test method

Details Test circuit, integrated circuit, and test method Test circuit, integrated circuit, and test method

2007-11-20

2007-11-20

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S765010

Reexamination Certificate

active

10765895

ABSTRACT:
A test circuit comprises a selector SEL1having a first input to which signals M1OUT from a macro block MB1are input and a second input to which test input signals TIN1and TIN2for a macro block MB2are input, and a selector SEL2having a first input to which a signal SQ from the SEL1is input and a second input to which a signal M2OUT from the MB2is input. In a first test mode in which the MB1is tested, the SEL1outputs the signals M1OUT from the MB1to a first input of the SEL2, and the SEL2outputs the signal SQ from the SEL1to the MB1. In a second test mode in which the MB2is tested, the SEL1outputs the test input signals TIN1and TIN2for the MB2to the MB2, and the SEL2outputs the signals M2OUT from the MB2as a test output signal TOUT for the MB2.

REFERENCES:
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patent: 6180426 (2001-01-01), Lin
patent: 6586266 (2003-07-01), Lin
patent: 2003/0199119 (2003-10-01), Lin
patent: 2005/0210347 (2005-09-01), Gossmann
patent: 10246755 (1998-09-01), None
patent: A 2001-183424 (2001-07-01), None
U.S. Appl. No. 10/766,038, filed Jan. 29, 2004, Nishida et al.

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