Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-08-04
2001-08-14
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06275963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a test circuit and a redundancy circuit for an internal memory circuit.
2. Description of the Background Art
Among prior-art test circuits and redundancy circuits for a memory circuit in a semiconductor integrated circuit device is a test circuit and a redundancy circuit shown in Japanese Patent Application Laid-Open Gazette 8-94718.
FIG. 43
is a circuit diagram showing a configuration of a prior-art scan flip flop
200
(hereinafter, sometimes abbreviated as “S-FF”) for a RAM test.
As shown in
FIG. 43
, a comparator
201
consists of an EX-OR gate
202
and a NAND gate
203
. One of inputs of the EX-OR gate
202
receives input data D and the other receives expected value data EXP, and one of inputs of the NAND gate
203
is connected to an output of the EX-OR gate
202
and the other receives a comparison control signal CMP. An output of the NAND gate
203
serves as an output of the comparator
201
.
The output of the comparator
201
is connected to one of inputs of an AND gate
204
. A selector
205
has a “0”-input receiving a serial input (data ) SI, a “1”-input connected to an output of the AND gate
204
and a control input receiving a test-mode signal TM
1
. The selector
205
outputs a signal given from the “1”/“0”-input based on “1”/“0” of the test-mode signal TM
1
through its output unit Y.
A selector
206
has a “0”-input receiving the input data D, and a “1”-input connected to the output unit Y of the selector
205
and a control input receiving a shift-mode signal SM. The selector
206
outputs a signal given from the “1”/“0” input based on “1”/“0” of the shift-mode signal SM through its output unit Y.
The D-FF (D-type flip flop)
207
has a D-input connected to the output unit Y of the selector
206
, a toggle input T receiving a timing signal (clock signal) T and a Q-output for outputting signals. The signals from the output unit Q are given outside and fed back to the other input of the AND gate
204
as a data output Q and a serial output (data) SO.
In this configuration, with the shift-mode signal SM of “0”, a normal operation starts to take the input data D into the D-FF
207
in synchronization with a timing signal T.
With the shift-mode signal SM of “1” and the test-mode signal TM
1
of “0”, the S-FF
200
enters a shift operation mode to take the serial input SI into the D-FF
207
in synchronization with the timing signal T.
With the shift-mode signal SM of “1” and the test-mode signal TM
1
of “1”, the S-FF
200
enters a test mode. In the test mode, supplying the comparison control signal CMP of “0” makes a test-invalid condition. The output of the comparator
201
forcedly becomes “1” and the Q-output of the D-FF
207
is fed back to the D-input to hold latch data of the D-FF
207
.
In the test mode, supplying the comparison control signal CMP of “1” makes a test-valid condition. The input data D is compared with the expected value data EXP and when agrees, the EX-OR gate
202
outputs “0” and the comparator
201
outputs “1” as comparison result data to hold the latch data of the D-FF
207
.
On the other hand, when disagrees, the EX-OR gate
202
outputs “1” and the comparator
201
outputs “0” as comparison result data to forcedly latch “0” into the D-FF
207
(to be reset).
FIG. 44
is a circuit diagram showing a configuration of a prior-art RAM with test circuit (showing only circuits connected to data outputs DO<
0
> to DO<
4
> of the RAM). As shown in
FIG. 44
, a test circuit
216
has a scan path for RAM test connecting in series five scan flip flops SFF<
0
> to SFF<
4
> each of which has the circuit configuration of FIG.
43
. Hereinafter, the scan flip flop SFF< > is sometimes abbreviated as SFF< >.
Specifically, the SFF<
4
> externally receives serial input data SIDO as its serial input SI and its serial output SO is connected to a serial input SI of the SFF<
3
>, and the SFF<
2
>, the SFF<
1
> and the SFF<
0
> are connected in series likewise. A serial output SO of the last-stage SFF<
0
> is externally outputted as serial output data SODO.
The SFF<
0
> to SFF<
4
> receive the shift-mode signal SM, the test-mode signal TM
1
, the expected value data EXP, the comparison control signal CMP and the timing signal T in common. Further, the SFF<
0
> to SFF<
4
> receive data outputs DO<
0
> to DO<
4
> as respective input data D and output respective data outputs Q as data outputs Q<
0
> to Q<
4
>.
With reference to
FIGS. 43 and 44
, a RAM test operation will be discussed below.
(1) Prior to the RAM test, in the shift mode {TM
1
=0, SM=1}, the serial input data SIDO (the serial input SI of the SFF<
4
>) of “1” is sequentially shifted to latch “1” into all the SFF<
0
> to SFF<
4
>. At this time, clocks for five cycles are needed as the timing signal T. As a result, all the serial outputs SO<
0
> to SO<
4
> of the SFF<
0
> to SFF<
4
> become “1”.
(2) In the test mode {TM
1
=1, SM=1}, the RAM test is executed on all the addresses. While test data are written or read out, the test-valid condition is made at a predetermined timing by appropriate control of the expected value data EXP and the comparison control signal CMP (when “1”, comparison is made).
If a RAM
211
has a failure, the output DO<i> (i=0 to 4) of the RAM
211
disagrees with the expected value data EXP in the test-valid condition. At this time, the comparison result data from the comparator
201
in the SFF<i> is “0” and the SFF<i> latches “0” therein in synchronization with the clock signal T to be reset.
For example, when a failure is found in the SFF<
2
> connected to the output data DO<
2
> of the RAM
211
, the serial output SO<
2
> becomes “0” (the serial outputs SO<
0
>, SO<
1
>, SO<
3
> and SO<
4
> are kept “1”).
(3) In the shift mode {TM
1
=0, SM=1}, the test result is sequentially outputted as the serial output data SODO (the serial output SO of the SFF<
0
>).
In the above example, “1”, “1”, “0”, “1” and “1” are outputted in this order as the serial output data SODO and the third serial output data SODO of “0” (indicative of failure) reveals existence of failure in the RAM
211
.
Since the prior-art test circuit for RAM in the semiconductor integrated circuit device performs the failure test for RAM as above, through observation of the serial output data SODO which are externally outputted in the stage (2) in the test mode, whether there is a failure of the data output DO<
0
> can be detected but whether there is a failure of the other data outputs DO<
1
>, DO<
2
>, DO<
3
> and DO<
4
> can not be detected. Therefore, the test in the stage (2) needs recognition on whether there is a failure of all the data outputs DO<
0
> to DO<
4
> in the stage (3) after executing the test on the data outputs DO<
0
> to DO<
4
> of all the addresses. That disadvantageously requires longer time than necessary to perform a test for detecting a defective RAM.
FIG. 45
is a circuit diagram showing a configuration of a semiconductor integrated circuit device having a RAM with test circuit and a redundancy circuit. In
FIG. 45
, a RAM with test circuit has a configuration where the RAM
212
with test circuit of
FIG. 44
is additionally provided with a redundancy circuit
213
.
As shown in
FIG. 45
, the serial outputs SO<
1
> to SO<
4
> of the scan flip flops SFF<
1
> to SFF<
4
> are taken into a register
214
and stored as store data G<
1
> to G<
4
>.
The store data G<
1
> to G<
3
> of the register
214
are applied to respective ones of inputs of AND gates
221
to
223
. The other input of the AND gate
221
is connected to an output
Maeno Hideshi
{overscore (O)}sawa Tokuya
Burns Doane , Swecker, Mathis LLP
De'cady Albert
Mitsubishi Denki & Kabushiki Kaisha
Ton David
LandOfFree
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