Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-06-27
2006-06-27
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07069486
ABSTRACT:
A scan path is formed by successively connecting the flip-flop FF11x located at the head of the xth stage to the flip-flop FF1mx located at the end of the xth stage in series. The scan path connects the scan input SIN with the input terminal of the flip-flop FF11n located at the head of the nth stage, and successively connects the flip-flop arranged in the second to (n−1)th stages in series, after restarting from the output terminal of the flip-flop FF1nm located at the end of the nth stage. The output terminal of the flip-flop FF1m(n−1) located at the end of the (n−1)th stage is connected with the input terminal of the flip-flop FF111located at the head of the first stage, and, finally, the output terminal of the flip-flop FF1m1located at the end of the first stage is connected with the scan output SOT.
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“IDDQ and AC Scan: The War Against Unmodelled Defects” by Maxwell et al. International Test Conference Proceedings Publication Date: Oct. 20-25, 1996, pp. 250-258 Inspec Accession Number: 5539851.
“The Testability Features of the 3rd Generation ColdFire(R) Family of Microprocessors” by Crouch et al. International Test Conference Proceedings Publication Date: Sep. 28-30, 1999, pp. 913-922 Inspec Accession Number: 6536446.
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Makita Yasuteru
Nagamine Ryouichirou
Britt Cynthia
De'cady Albert
McGinn IP Law Group PLLC
NEC Electronics Corporation
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