Test circuit provided with built-in self test function

Details Test circuit provided with built-in self test function Test circuit provided with built-in self test function

2006-09-26

2006-09-26

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S735000

Reexamination Certificate

active

07114113

ABSTRACT:
A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence
on-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.

REFERENCES:
patent: 5640401 (1997-06-01), Yamada
patent: 6009028 (1999-12-01), Akiyama
patent: 6343366 (2002-01-01), Okitaka
patent: 6744272 (2004-06-01), Ernst et al.
patent: 10-199294 (1998-07-01), None
patent: 2002-174662 (2002-06-01), None

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