Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-02-05
2000-07-18
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
060922273
ABSTRACT:
A test circuit includes a writing unit that outputs m-bit data captured upon receipt of a clock signal, branches the m-bit data n identical m-bit data signals, and stores the n m-bit data signals in a memory device. A function determining unit reads the n m-bit data signals from the memory, compares one of the n m-bit data signals to an m-bit expected value, and determines coincidence or non-coincidence between the n m-bit data signal and an expected value.
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Hatakenaka Makoto
Kitaguchi Akira
Matsuo Masaaki
Saitoh Tsuyoshi
Shiroshima Kiyoyuki
Cady Albert De
Chase Shelly A
Mitsubishi Denki & Kabushiki Kaisha
Mitsubishi Electric System LSI Design Corporation
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