Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-08-23
2005-08-23
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
06934898
ABSTRACT:
Among the embodiments of the present invention is a technique that includes executing a first protocol on test bus (40) in accordance with an established test standard to operate a first topology of several test ports (70) and activating to a shadow controller (60) by executing a second protocol on test bus (40). Operation of the test ports (70) is suspended during execution of the second protocol. During activation, the shadow controller (60) can be used to set-up a second topology of one or more of test ports (70) for operation after the test port suspension is discontinued.
REFERENCES:
patent: 5483518 (1996-01-01), Whetsel
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5640521 (1997-06-01), Whetsel
patent: 5724505 (1998-03-01), Argade et al.
patent: 5781560 (1998-07-01), Kawano et al.
patent: 5862152 (1999-01-01), Handly et al.
patent: 5915083 (1999-06-01), Ponte
patent: 5928374 (1999-07-01), Shimizu et al.
patent: 5935266 (1999-08-01), Thurnhofer et al.
patent: 5996081 (1999-11-01), Shim
patent: 6018815 (2000-01-01), Baeg
patent: 6055656 (2000-04-01), Wilson, Jr. et al.
patent: 6078979 (2000-06-01), Li et al.
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6142683 (2000-11-01), Madduri
patent: 6158032 (2000-12-01), Currier et al.
patent: 6175914 (2001-01-01), Mann
patent: 6185732 (2001-02-01), Mann et al.
patent: 6189140 (2001-02-01), Madduri
patent: 6202172 (2001-03-01), Ponte
patent: 6363464 (2002-03-01), Mangione
patent: 6625559 (2003-09-01), Helder
patent: 2001/0010083 (2001-07-01), Satoh
patent: 2001/0034598 (2001-10-01), Swoboda
Whetsel, L., “An IEEE 1149.1 Based Test Access Architecture for ICS with Embedded Cores”, Jul. 1997, Conf. 28, New York, NY USA.
Koninklijke Philips Electronics , N.V.
Ton David
Zawilski Peter
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