Test circuit and test method for testing semiconductor chip

Details Test circuit and test method for testing semiconductor chip Test circuit and test method for testing semiconductor chip

1997-12-23

2000-06-20

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714727, 714724, 714729, G01R 3128

Patent

active

060790393

ABSTRACT:
In a test circuit, both a boundary scan test and an internal scan test are carried out. Such a test circuit has at least one test terminal for the boundary scan test. In this event, a test clock signal is given to the test terminal. Further, the test circuit has a first clock generating circuit and a second clock generating circuit. The first clock generating circuit generates a first clock signal for the boundary scan test based upon the test clock signal. On the other hand, the second clock generating circuit generates a second clock signal for the internal scan test based upon the test clock signal. Thus, the first clock signal for the boundary scan test and the second clock signal for the internal scan test are made on the basis of the same clock signal (the test clock signal). As a result, the internal scan test can be performed by the same sequence with the boundary scan test without an increment of test terminals.

REFERENCES:
patent: 5530706 (1996-06-01), Josephson et al.
patent: 5663966 (1997-09-01), Day et al.
patent: 5673273 (1997-09-01), Almy
patent: 5701308 (1997-12-01), Attaway et al.
patent: 5748645 (1998-05-01), Hunter et al.
IEEE, Standard 1149.1, 1990, p. 5-1 and Appendix A-1-A-2.

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