Test circuit method and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S742000, C714S724000

Reexamination Certificate

active

06898748

ABSTRACT:
A test circuit for integrated circuit devices shortens test times, and reduces the length of the test pattern and the number of external terminals. The test circuit is provided between first and second target circuits, and incorporates a first selection section for selecting one of a first output signal from the first target circuit, a second output signal from the second target circuit, and a test signal indicating a test pattern input via a test pattern input terminal. A temporarily data storage section stores the signal selected by the first section, and a second selection selects one of temporarily stored data or the second output signal. The results are provide to the first target circuit. A third selecting section is provided; for selecting one of the temporarily stored data signal or the first output signal, and providing the selected signal to the second target circuit.

REFERENCES:
patent: 5627841 (1997-05-01), Nakamura
patent: 5680406 (1997-10-01), Nakamura
patent: 5710867 (1998-01-01), Giacalone et al.
patent: 5768289 (1998-06-01), James
patent: 5847561 (1998-12-01), Whetsel
patent: 5960008 (1999-09-01), Osawa et al.
patent: 6000051 (1999-12-01), Nadeau-Dostie et al.
patent: 6079039 (2000-06-01), Nakamura
patent: 6122762 (2000-09-01), Kim
patent: 6134675 (2000-10-01), Raina
patent: 6189128 (2001-02-01), Asaka
patent: 6223315 (2001-04-01), Whetsel
patent: 6324662 (2001-11-01), Haroun et al.
patent: 10-078475 (1998-03-01), None
patent: 11-202031 (1999-07-01), None

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