Test circuit and system for interconnect testing of high-level p

Details Test circuit and system for interconnect testing of high-level p Test circuit and system for interconnect testing of high-level p

1997-11-24

2000-02-22

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

06029261&

ABSTRACT:
The invention relates to a test circuit and a test system which provides interconnect test capability for modules and boards. The test circuit comprises a plurality of scan chains, including a plurality of registers. The registers in each module or board are logically sorted such that identical registers are arranged successively.

REFERENCES:
patent: 4428060 (1984-01-01), Blum
patent: 5239262 (1993-08-01), Gruetzner et al.
patent: 5444715 (1995-08-01), Gruetzner et al.
patent: 5477548 (1995-12-01), Beenker et al.
patent: 5497378 (1996-03-01), Amini et al.

Affiliated with

Also associated with

Rating

Test circuit and system for interconnect testing of high-level p does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test circuit and system for interconnect testing of high-level p, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test circuit and system for interconnect testing of high-level p will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-529987