Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-06-24
2008-06-24
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S016000, C326S039000
Reexamination Certificate
active
07392446
ABSTRACT:
Testing an integrated circuit having programmable logic is described. Programmable logic is configured as a daisy-chain of registers (310-1through310-(N+1)) in a closed input/output loop to register a logic 1 and logic 0s. The logic states are circulated around the closed input/output loop. Operation of output blocks (210-1through210-N) is controlled responsive to a series of outputs (316-1through316-N) provided from a portion of the daisy-chain of registers (310-1through310-N) to selectively place an output block of output blocks (210-1through210-N) in an output mode responsive to the logic 1 output in the series of outputs while leaving the output blocks remaining in a non-output mode responsive to the logic 0s in the series of outputs. The output blocks (210-1through210-N) are commonly coupled at an output node (212) for coupling to a single test channel, as only one output block is in the output mode at a time.
REFERENCES:
patent: 5773994 (1998-06-01), Jones
patent: 7010667 (2006-03-01), Vorbach et al.
patent: 2005/0138500 (2005-06-01), Sul et al.
patent: 2005/0262396 (2005-11-01), Woodward et al.
“Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)” by Swift et al. IEEE Transactions on Nuclear Science, Publication Date: Dec. 2004 vol. 51, Issue: 6 On pp. 3469-3474 ISSN: 0018-9499 Inspec Accession No. 8225503.
Xilinx, Inc.; “The Programmable Logic Data Book 2000”; Published Apr. 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 3-75 through 3-96.
Sadler Brian
Simmons Tuyet Ngoc
Britt Cynthia
Webostad W. Eric
Xilinx , Inc.
LandOfFree
Test channel usage reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test channel usage reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test channel usage reduction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2799824