Test circuit for exposing higher order speed paths

Details Test circuit for exposing higher order speed paths Test circuit for exposing higher order speed paths

2001-03-20

2003-12-30

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C713S500000

Reexamination Certificate

active

06671848

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to test circuits and, more particularly, to clock control during testing.
2. Description of the Related Art
During the manufacturing life cycle of an electrical circuit, there may be many levels of circuit testing. For example, during the design phase, circuit designers may initiate several test simulations on their designs to ensure that the designs meet a set of specifications prior to releasing their designs to the next stage of manufacturing. Additionally, a test or product engineer may develop an extensive suite of test programs that run on manufacturing testers. These test programs are typically designed to screen out circuit defects that may have occurred during the manufacturing process.
In addition, once a circuit design has completed an initial manufacturing process it is often tested using a specialized test program that is commonly referred to as a characterization program. Many characterization programs are developed to detect not only manufacturing defects, but also any design flaws that may have been inadvertently designed into the circuit and escaped earlier simulations. Characterization programs may therefore need to test a circuit to its physical limits. In contrast, a production test program may be designed to only test a circuit within a prescribed set of limits. The limits are in many cases determined through the use of the characterization program. A characterization program may repetitively exercise a circuit using the same tests while varying such parameters as supply voltage, applied clock frequency and ambient operating temperature. In this way, the circuit's operation may be characterized across a wide range of voltage, frequency and temperature.
When a defect is detected or an operational limit is reached during characterization, in many cases the characterization test program or test patterns are modified to continue characterization despite the defect or operational limit. However, if the circuit is an integrated circuit, there may be many factors that make it difficult to continue the characterization process by making program and pattern modifications alone. For example, the type of integrated circuit, the available test modes and the available external circuit package leads may make program and pattern changes alone impractical or impossible. This may be particularly true for frequency dependent failures in circuits containing a clock generator circuit such as phased lock loop (PLL) circuit. In some cases, the circuit defect may have to be fixed and the circuit sent through the manufacturing process again before any higher order defects may be detected. This may become an expensive iterative process until all the defects that prevent characterization are fixed. Thus, an efficient method of allowing circuit testing to continue despite circuit defects is desired.
SUMMARY OF THE INVENTION
Various embodiments of a test circuit for exposing higher order speed paths are disclosed. In one embodiment, a test circuit includes a clock generation circuit coupled to a test clock control unit. The clock generation circuit is configured to receive an input clock signal and to generate an output clock signal. The test clock control unit is configured to selectively provide a user programmable test vector or a fixed test vector to control the generation of the output clock signal by the clock generation circuit depending upon a state of a first mode select signal.
In one particular implementation, the user programmable test vector and the fixed test vector are multiple-bit binary values. The test clock control unit may be configured to store the user programmable test vector in a programmable register. In other implementations, the test clock control unit may be configured to select either of the user programmable test vector or the fixed test vector using a first plurality of multiplexers, one for each bit of the user programmable test vector and the fixed test vector. The input select of each of the first plurality of multiplexers may be controllable by the first mode select signal.
In other implementations, the test clock control unit may be configured to selectively provide a multiple-bit bypass test vector to control the generation of the output clock signal by the clock generation circuit depending upon a state of a second mode select signal. In addition, the test clock control unit may be configured to serially shift each bit of the user programmable test vector, the fixed test vector and the bypass test vector to the clock generation circuit using a shift register.


REFERENCES:
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patent: 6170069 (2001-01-01), Ohtani et al.
patent: 6510534 (2003-01-01), Nadeau-Dostie et al.
patent: 6571357 (2003-05-01), Martin et al.

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