LandOfFree - US Patents - Listing for Error detection/correction and fault detection/recovery,Pulse or data error handling,Digital logic testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Software testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Software-based simulation system capable of simulating the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Spatial and temporal alignment of a scan dump for debug of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Speed-signaling testing for integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Split L2 latch with glitch free programmable delay

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Squence control circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

SRAM that can be clocked on either clock phase

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

SSD test systems and methods

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Star-I: scalable tester architecture with I-cached SIMD technolo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

STAR-I: scalable tester architecture with I-cached SIMD technolo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Start/stop circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Start/stop circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

State relaxation based subsequence removal method for fast stati

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Static test sequence compaction using two-phase restoration and

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Static timing analysis approach for multi-clock domain designs

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Statistical decision system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Stimulus extraction and sequence generation for an electric...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Stimulus generation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Streamlined LASAR-to-L200 post-processing for CASS