Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-08-15
2004-08-24
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S763010, C702S118000
Reexamination Certificate
active
06782500
ABSTRACT:
FIELD
This invention relates to the field of testing integrated circuits. More particularly the invention relates to a system for applying the failure limits for various electronic characteristics of an electronic circuit at a point in time after the electronic characteristics of the integrated circuits have been sensed.
BACKGROUND
Integrated circuit fabrication is an extremely complex process. Therefore, the various processes used to fabricate integrated circuits are often categorized in some manner, in order to simplify the description of the various phases of fabrication. For example, the various steps employed to create the integrated circuits while they are disposed upon a monolithic substrate is often called wafer processing. After wafer processing, the devices are tested for conformance to predicted parameters in what may be called wafer testing. After wafer testing the circuits are diced and then integrated circuits that have been binned as “good” circuits are packaged.
Typically, an individual integrated circuit on the wafer is binned as good or bad during wafer testing. The wafer testing equipment is programmed to run a regimen of tests on each integrated circuit by applying known electrical input on the electrical contact pads of the integrated circuit. The electrical response of the integrated circuit to the input is sensed and measured at the output electrical contact pads of the integrated circuit. The measured output values are compared to a set of predetermined expected output values, and if any of the measured output values violate the corresponding predetermined expected output values, such as by being either greater than or less than the predetermined expected output value as the case may be, then the integrated circuit is binned by the automated wafer tester as bad.
When the circuit is designated as bad, a drop of ink is typically placed atop the circuit by the wafer tester. After the integrated circuits are diced, the pick and place unit that removes the individual integrated circuits and places them into packages detects the ink drop on the bad integrated circuits, and skips them so that they are not placed into packages and processed further. The inked integrated circuits that are left on the dicing tape by the pick and place are then discarded.
The predetermined expected output values are typically determined by correlating output values for a large number of packaged devices. The packaged devices are tested to see whether they function properly or whether they fail prematurely. The output values for those devices that either do not function at all or fail prematurely are studied, and a predetermined expected output value is selected such that most of the devices with output values that do not violate the predetermined expected output value function properly for a desired length of time, and most of the devices with output values that do violate the predetermined expected output value either do not function properly for the desired length of time or do not function properly.
Unfortunately, this method of setting expected output values is extremely imprecise. Some of the devices that violate the predetermined expected output value function properly for the desired length of time, and some of the devices that do not violate the predetermined expected output value do not function properly for the desired length of time.
Thus, this traditional method of wafer testing and binning is extremely inflexible and does not account for the individual characteristics of an integrated circuit on the wafer. For example, the automated wafer tester has no way of knowing whether the output value received from the tested integrated circuit is a value that should be expected from the integrated circuit, based on the specific processing received by that integrated circuit. Thus, some amount of integrated circuits that are actually good are binned as bad, and some amount of integrated circuits that are actually bad are binned as good. Further, once the automated wafer tester bins a specific integrated circuit as bad and places an ink drop on it, there is no easy way to go back to and review the test data and reclaim the integrated circuit.
What is needed, therefore, is a system to bin integrated circuits in response to binning limits that are based upon expected output values that take into account specific processing received by the integrated circuits, rather than upon predetermined expected output values that do not take into account specific processing. Further, a system is needed that provides flexibility in binning the integrated circuits in response to the binning limits.
SUMMARY
The above and other needs are met by a method for processing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a failure classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.
In this manner, the processing of the integrated circuits is taken into account. This is accomplished by using a difference between the mathematically manipulated value and the sensed value for each individual integrated circuit for the determination as to whether the individual integrated circuit is binned as a passing or failing device, rather than binning the integrated circuit based on whether it violates a predetermined expected value. In a preferred embodiment of the method described above, all of the values for the integrated circuits on a wafer are sensed and output prior to using them in the mathematical manipulations. It is also preferable that the steps of the method up to and including the step of recording the output from the integrated circuits are accomplished by a wafer tester, and the subsequent steps of the method are accomplished by an off-line binner. In this manner, a great degree of flexibility is provided by the method.
Aspects of the invention are also embodied in an instruction set residing on a digital recording media. The instruction set enables a computing device to receive and analyze an ordered data set that contains individual data points from a wafer tester, where the individual data points relate to electrical characteristics of integrated circuits. The instruction set also enables the computing device to associate failure codes with selected ones of the integrated circuits. The instruction set includes input instructions for receiving the ordered set of data from the wafer tester. Computational instructions mathematically manipulate the ordered set of data to produce a reference value, and comparison instructions compare the individual data points to the reference value to identify individual data points that differ from the reference value by more than a given amount. Binning instructions associate the failure codes with the integrated circuits that have individual data points that differ from the reference value by more than the given amount, and output instructions output the failure codes with the ordered data set.
In a preferred embodiment, the reference value is the median of the ordered set of data, and the standard deviation of the ordered set of data is used as the basis for determining the given amount by which the integrated circuits are binned.
REFERENCES:
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5889408 (1999-03-01), Mi
Bockelman Daniel R.
Cota Kevin
Daasch W. Robert
Madge Robert J.
McNames James N.
Britt Cynthia
De'cady Albert
LSI Logic Corporation
Luedeka Neely & Graham PC
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