Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-13
2002-11-19
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000
Reexamination Certificate
active
06484281
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88117223, filed Oct. 6, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer technology, and more particularly, to a software-based simulation system which is capable of simulating the combined functionality of a South Bridge test module and a North Bridge test module with only one of the two test modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both.
2. Description of Related Art
A simulating North Bridge chipset is a test circuit that is specifically designed for use on a computer motherboard for simulating the functionality of an actual Host-to-PCI bridge controller, while a simulating South Bridge chipset is another type of test circuit that is specifically designed for simulating the functionality of the various kinds of actual peripheral devices connected to the motherboard via such interfaces as ISA (Industry Standard Architecture), IDE (Integrated Device Electronics), USB (Universal Serial Bus), and AC-Link interfaces.
Before tape-out, an IC chipset is typically tested through simulation for the purpose of checking whether the IC chipset would function properly. When the design of an IC chipset is completed, the designed circuit architecture is mathematically simulated to check whether it would functionally meet the design specifications. Then, after the layout is completed, timing factors such as delays and electrical characteristics are added to the circuit for a second simulation.
The testing for an IC chipset can be carried out in two ways: a hardware-based testing method and a software-based testing method. By the hardware-based testing method, a prototype device is made in accordance with the designed circuit diagram, which is then mounted on a customized hardware circuit board made to function in conjunction with the tested device. The hardware-based testing method can check whether the designed IC chipset would function properly when practically implemented.
One advantage to the hardware-based testing method is that it is a fast testing procedure so that the testing can be completed in a short time. One drawback of the hardware-based testing method, however, is that it requires the settings of various parameters and mounting of various circuit components for the testing of different types of IC chipsets, and this work would typically require a team of more than 20 technicians to achieve. This makes the hardware-based testing method quite laborious and time-consuming to achieve, and is therefore quite cost-ineffective to implement.
The software-based testing method, on the other hand, performs the testing through a simulation software program, which is coded by a special programming language, such as Verlog code, for modeling the designed IC chipset. The simulation program can compute for the input/output characteristics of the designed IC chipset.
A conventional setup for implementing the software-based testing method is to use a North Bridge test module and a South Bridge test module. The North Bridge test module includes a simulation circuit that is designed to simulate the functionality of a Host-to-PCI bridge controller, and further includes a CPU, a memory unit, an AGP device, and a PCI bus. The South Bridge test module includes a simulation circuit that is designed to simulate a PCI-to-ISA bridge controller, and further includes an IDE interface, an AC-Link interface, a USB interface, an ISA bus, a PCI bus, an LPC bus, and an SM bus. The South Bridge chipset is used to test the peripheral devices connected via these interfaces thereto.
FIG. 1
is a schematic block diagram showing a conventional chipset system including the North Bride and South Bridge. In
FIG. 1
, the system includes a North Bride module, a South Bridge module, and a PCI bus
30
between them. The North Bridge module includes a central processing unit (CPU)
5
, an advanced graphics port (AGP)
10
, a memory unit
15
, a North Bridge test circuit
20
, and a host bus
25
. The South Bridge includes a South Bride test circuit
60
, an LPC bus
65
, a system manager (SM) bus
70
, an ISA bus, a connection means for connecting the LPC bus
65
, the SM bus
70
, and the industry standard architecture (ISA) bus to the South Bridge test circuit
60
, and a connection means for connecting an UBS device
55
, an IDE device, and codec
50
to the South Bridge test circuit
60
.
The connection means for connecting LPC bus
65
, SM bus
70
, and ISA bus to the South Bridge test circuit
60
includes a LPC device
68
, an SM master
72
, an SM slave
74
, and ISA master
82
, and an ISA slave
84
.
The North Bride module and the South bridge module in
FIG. 1
is coupled together through the PCI bus
30
. The PCI bus also has couplings with a PCI master
35
and a PCI slave
40
. The South Bridge circuit
60
is used to simulate a PCI/ISA bridge controller, and the North Bridge test circuit
20
is used to simulate a PCI/HOST bridge controller.
One advantage to the software-based testing method utilizing the South Bridge chipset and the North Bridge chipset is that it requires a reduced cost to implement as compared to the hardware-based testing method. One drawback to this software-based testing method, however, is that it is quite time-consuming since it requires the CPU to spend much time on the computation for the input/output response of each constituent component in the tested chipset.
Since the South Bridge chipset and the North Bridge chipset are both very complex in architecture, they are typically designed by two different teams of engineers. However, since the South Bridge chipset and the North Bridge chipset should work together to implement the software-based testing method, they must be finished in design and manufacture substantially at the same time. In the event that one team is behind schedule, the other team may waste time in waiting. This makes the project management quite difficult.
In summary, the prior art has the following drawbacks.
First, the hardware-based testing method requires a large amount of labor and time for system setup and parameter setting, and therefore is quite costly to implement.
Second, the software-based testing method is quite slow in speed since it would spend much time on the computation for the input/output response of each constituent component in the chipset including CPU, ISA devices, and memory.
Third, the software-based testing method would cause the project management quite difficult since the South Bridge chipset and the North Bridge chipset should be finished in design and manufacture substantially at the same time.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a software-based simulation system which can be used in conjunction with either the South Bridge chipset or the North Bridge chipset, but can nonetheless perform the combined functionality of the South Bridge chipset and the North Bridge chipset.
It is another objective of this invention to provide a software-based simulation system, which allows the testing to be completed in a shorter time than the prior art, so that the testing can be more efficiently implemented.
It is still another objective of this invention to provide a software-based simulation system, which allows the testing to be implemented in a more cost-effective manner than the prior art.
It is yet another objective of this invention to provide a software-based simulation system, which allows the project management for its design and implementation to be easier than the prior art.
In accordance with the foregoing and other objectives, a novel software-based simulation system is proposed. The software-based simulation system of the invention is characterized in that it is based solely on either the South Bridge chipset or the North Bridge chipset but can nonetheless provide the combined fuinctionality of both chipsets. This feature allows the benefits of reduced testing time,
Chang Nai-Shung
Lai Jiin
Wang Hsuan-Yi
J.C. Patents
Ton David
Via Technologies Inc.
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