SRAM that can be clocked on either clock phase

Details SRAM that can be clocked on either clock phase SRAM that can be clocked on either clock phase

1998-07-31

2001-07-10

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000, C713S600000

Reexamination Certificate

active

06260164

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a functional unit in a single clock chip design that contains a scan path. More particularly, the present invention relates to an SRAM in a single clock chip design that contains a scan path which can be clocked on either rising edge or falling edge of the clock.
BACKGROUND OF THE INVENTION
In designing large scale integration (LSI) circuits or very large scale integration (VLSI) circuits, one important step is to incorporate testing circuits for the designs. The principle is to proceed testing methods concurrently with the architectural considerations of the designs as opposed to be left until fabricated chip or components of the chip have been made. This manufacturing test principle has been well recognized by the LSI and VLSI design industry.
The testing of large scale integration (LSI) packages, very large scale integration (VLSI) packages, and application-specific integrated circuits (ASIC) has become increasingly important as these components and circuits continue to increase in gate densities. One existing built-in self-test system is called Array Built-In Self-Test (ABIST). ABIST is accomplished using an ABIST controller which sends address and data to all the arrays of functional logic units and receives output data from the arrays at the same time via scanning. The outputted data is compared with the expected data so as to determine the accuracy of the chip design and the performance thereof The ABIST controller does not differentiate or compensate for the different arrays which are clocked in different phases, i.e. clocked at the rising edge or at the falling edge.
In a single clock chip design, depending upon the functional requirements of the chip design, a functional array, such as an SRAM, needs to be clocked on different phases of the clock, for example, a Dcache array and an Icache array. The Dcache may be clocked in one phase of the clock (e.g. the rising edge of the clock), and the Icache may be clocked in the other phase of the clock (e.g. the falling edge of the clock). Accordingly, the two arrays are generally the same except their clock phases.
In addition, the SRAM is designed to be tested by the ABIST. In general, the SRAM includes a primitive SRAM (pure SRAM logic) and a set of scan latches at the input and output of the SRAM array. These latches are used for the ABIST test. The ABIST sends scan data to the scan latches during a test. The scan latches are arranged in a scan chain or scan ring and configured by a plurality of latch pairs K
0
/K
1
. In general, the K
0
latch and K
1
latch are the same except that they latch their input data at different edge of the clock. The K
0
latch is latched at the rising edge of the clock, i.e. the scan data is latched by the K
0
latch at the rising edge of the clock. The K
1
latch is latched at the falling edge of the clock, i.e. the scan data is latched by the K
1
latch at the falling edge of the clock. In a normal clock cycle (i.e. CLK), the K
0
latch latches a half cycle ahead of the K
1
latch, i.e. the latch pair being in an order of K
0
/K
1
. Alternatively, in a clock cycle −CLK, the K
0
latch latches a half cycle behind the K
1
latch, i.e. the latch pair being in an order of K
1
/K
0
.
In a traditional single clock chip design, an SRAM clocked at the rising phase of the clock (e.g. Dcache array) is referred to K
0
array, and an SRAM clocked at the falling phase of the clock (e.g. Icache array) is referred to K
1
array.
FIG. 1
illustrates the K
0
and K
1
arrays. The ABIST sends Scan-In data to the K
0
and K
1
arrays and receives Scan-Out data from the K
0
and K
1
arrays. For the purpose of illustration, scan latch pairs K
0
/K
1
(LCH
1
, LCH
2
, . . . LCHN) are only shown at the input of the K
0
and K
1
arrays. In general, the scan latch pairs K
0
/K
1
are also connected to the output of the K
0
and K
1
arrays. As mentioned above, the K
0
and K
1
arrays are identical except their clock phase, K
0
array being clocked at the rising edge of the clock, and the K
1
array being clocked at the falling edge of the clock. Therefore, to reduce the design complication and cost, there is a need to design a scannable, single array which can be clocked on either phase of the clock so as to satisfy functional requirements for different types but identical arrays (e.g. Dcache and Icache). However, as mentioned above, to simply invert the clock (i.e. −CLK) into a single array to obtain the second type of array (i.e. K
1
array) would reverse the scan latch pairs K
0
and K
1
(i.e. in an order of K
1
/K
0
) in the array. The reverse of K
0
/K
1
scan latches causes latch phase problems in interfacing outside the array. Specifically, the array driven by CLK has a latch phase K
0
/K
1
—K
0
/K
1
in interfacing outside the array (the first K
0
/K
1
pair is outside the array, and the second K
0
/K
1
is inside the array). However, the array driven by −CLK has a latch phase K
0
/K
1
—K
1
/K
0
in interfacing outside the array. This type of latch phase discontinuance cannot be tolerated in a chip design. Therefore, traditionally, two similar arrays are designed for an SRAM to satisfy functional requirements, for example Dcache and Icache. As a result, it requires extra design effort and cost. Further, the resource for designing the SRAM increases significantly.
In addition, as mentioned above, the scan latches K
0
and K
1
in a latch pair are the same except that they latch data at different phase of the clock. By simply inverting the clock into the array to obtain the second type of array (i.e. K
1
array), the scan latches K
0
/K
1
are made backwards, i.e. the KO latch is clocked at the falling edge of the clock, and the K
1
latch is clocked at the rising edge of the clock. Since the ABIST is generally not designed to compensate for the changes due to the changes of K
0
/K
1
latch pair, the scan may not be accomplished by using a single controller which sends address and data to all the arrays and receives output data from the arrays at the same time via scanning. As a result, similar arrays are designed for the ABIST.
FIG. 1
shows scan paths of two similar K
0
,K
1
arrays in a traditional single clock chip design. The ABIST controls both K
0
and K
1
arrays. In each of the K
0
and K
1
arrays, latch pairs LCH
1
, LCH
2
, . . . LCHN are arranged in an order of K
0
/K
1
. The test tool of the ABIST sends the Scan-in data to the K
0
,K
1
arrays and receives the Scan-out data from the K
0
,K
1
arrays. In addition, a scan/hold/enable controller determines whether the arrays are under a scan mode or a functional mode.
FIG. 1
only shows the scan path of the arrays. Further, a clock controller controls the free-running clock CLK and determines which array(s) should be activated for operations such as a scan operation or a functional operation, etc.
Therefore, there is a need to design a scannable, single array which can be clocked on either clock phase. There is also a need to design an improved SRAM which can be clocked on either clock phase so as to satisfy functional requirements, e.g. Dcache and Icache. The present invention provides a solution to the above and other problems and offers other advantages over the prior art.
SUMMARY OF THE INVENTION
The present invention relates generally to a functional unit in a single clock chip design that contains a scan path. More particularly, the present invention relates to an SRAM in a single clock chip design that contains a scan path which can be clocked on either rising edge or falling edge of the clock.
In one embodiment of the present invention, a functional unit, such as an SRAM, includes a clock signal and a plurality of latches for scanning that can be clocked on either phase of the clock signal.
Still in one embodiment, a positive or negative clock signal is chosen as input to an array which is referred to as K array having scan latches R
0
/R
1
. If the clock signal is positive (i.e. CLK), the scan latches R
0
/R
1
of the K array are the same as and fu

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