Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-08-03
2000-07-25
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
3241581, G01R 3128
Patent
active
060947357
ABSTRACT:
An integrated circuit has digital logic that supports two or more different processing speeds and two or more different data rates that are distinguished by each data rate having a data prefix at a different common-mode voltage. For normal processing, the integrated circuit has one or more comparators that compare the average signal voltage level with one or more reference voltages to determine the data rate. According to one embodiment of the invention, one or more muxes are configured between the comparators and the digital logic. These muxes can be controlled during testing to by-pass the operations of the comparators to pass specified digital codes to the digital logic to simulate the operations of the comparators. In this way, the different processing speeds of the digital logic can be tested without having to build special automatic test equipment to support all of the different possible voltage levels corresponding to the different supported data rates.
REFERENCES:
patent: 4635247 (1987-01-01), Tejima
patent: 4792951 (1988-12-01), Nielsen
patent: 5049814 (1991-09-01), Walker, III et al.
patent: 5590137 (1996-12-01), Yamashita
Cole Clifford B.
Coyne Joseph D.
Patel Bijit T.
Shinkarovsky Michael
Lucent Technologies - Inc.
Mendelsohn Steve
Nguyen Hoa T.
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