Split L2 latch with glitch free programmable delay

Details Split L2 latch with glitch free programmable delay Split L2 latch with glitch free programmable delay

2007-11-06

2007-11-06

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

11054311

ABSTRACT:
A programmable delay circuit that delays the C2clock signal by a variable amount that allows the output from the L1latch to be captured even when there is a large delta between the L1latch and its L2latch. This allows the C2signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C2clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C2is controlled to maintain a constant C2duty cycle.

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patent: 6192092 (2001-02-01), Dizon et al.
patent: 6380785 (2002-04-01), Fisher
patent: 6381704 (2002-04-01), Cano et al.
patent: 6701466 (2004-03-01), Fiedler

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