Static timing analysis approach for multi-clock domain designs

Details Static timing analysis approach for multi-clock domain designs Static timing analysis approach for multi-clock domain designs

2006-11-07

2006-11-07

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C716S030000

Reexamination Certificate

active

07134062

ABSTRACT:
A method for analyzing a circuit design is disclosed. The method generally includes the steps of (A) determining a plurality of paths from a first clock at a first location to a plurality of second clocks at a plurality of second locations in the circuit design, (B) calculating a plurality of delays along the paths and (C) calculating a plurality of latencies with respect to the first clock for the second clocks using the delays.

REFERENCES:
patent: 5761097 (1998-06-01), Palermo
patent: 5771375 (1998-06-01), Mains
patent: 6272668 (2001-08-01), Teene
patent: 6609241 (2003-08-01), Yonemori
patent: 6658635 (2003-12-01), Tanimoto
patent: 6693890 (2004-02-01), Yick et al.
patent: 6851098 (2005-02-01), Schultz
patent: 6874108 (2005-03-01), Abramovici et al.
“Standard Delay Format Specification”, Version 3.0, May 1995, Open Verilog International, 104 pages.
“Prime Time Specific Setup”, Oct. 1999, LSI Logic Corporation, Paragraphs, 9-11 and 18-19, 17 pages.

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